1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of fabrication of capacitors in semiconductor dies.
2. Background Art
Metal-oxide-metal (MOM) capacitors have been used extensively in the fabrication of integrated analog and mixed signal circuits on semiconductor dies. A MOM capacitor typically includes an oxide dielectric situated between adjacent metal plates, which form the electrodes of the MOM capacitor. Conventionally, MOM capacitors are fabricated on semiconductor dies during back-end-of-line (BEOL) processing.
In the conventional approach, MOM capacitors are fabricated in the otherwise unused space available between routing metallization layers in a semiconductor die, during BEOL processing. However, the low dielectric constant (low-κ) of the dielectric materials typically present between routing metallization layers, such as materials having dielectric constants less than 3.0, for example, result in conventional MOM capacitors having relatively low capacitance densities. Although specialized dielectric materials can be use to form the MOM capacitor dielectric during BEOL, that alternative approach can require additional process steps and masks beyond those normally required for complementary metal-oxide-semiconductor (CMOS) fabrication process flows, which can undesirably increase manufacturing cost. Moreover, although it is desirable in principle to fabricate MOM capacitors having higher capacitance densities, situating such MOM capacitors between routing metallization layers formed over the device layer in which active devices are fabricated can adversely affect device performance, such as the speed of CMOS logic devices, for example.
Thus, there is a need to overcome the drawbacks and deficiencies in the conventional art by providing a MOM capacitor capable of achieving a higher capacitance density while being compatible with standard CMOS fabrication materials and process flows.